Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience with hardware description languages like System Verilog and VHDL
- Experience with full cycle of design verification: plan, env/test developing, bug/cov closure.
- Master's degree in Electrical Engineering, Computer Science, or related field.
- ISS (instruction set simulator) based CPU DV experience, developing ISA model such as RISC-V spike model or ARM ASL based simulators.
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About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Collaborate with design to create test plan cover specific part of the CPU.
- Generate test cases to meet the needs of the verification.
- Debug failures and analyze coverage, and co-work with designers to fix them.
- Track and report the verification process using metrics like bugs and coverage.
- Improve verification methodology/environment strategically.