Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Chemical Engineering, Physics, Chemistry, Material Science, a related field, or equivalent practical experience.
- 4 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
- 3 years of experience in software development, or 1 year of experience with an advanced degree.
- Experience with one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
- Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.
- Experience in low power design Implementation including Common Power Format (CPF)/Unified Power Format (UPF), multi-voltage domains, power gating.
- Experience in floor planning and block integration.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Develop all aspects of ASIC RTL2GDS implementation for high Power Performance Area (PPA) designs.
- Manage block and full-chip level physical implementation.
- Define and implement innovative schemes and design methodologies to improve performance and power.
- Drive physical implementation steps including synthesis, floor-planning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification on blocks, subsystems or full-chip.
- Work with logic designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure.