Physical Design Implementation Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 2 years of experience in physical design.
• Experience with one or more synthesis/Place and Route (PnR) tools (e.g., Genus, Innovus, Design Compiler (DC), Integrated Circuit Compiler (ICC)).

Preferred qualifications:

• Experience in low-power design implementation, including Unified Power Format (UPF), Common Power Format (CPF), multi-voltage domains, and power gating.
• Experience with ASIC design flows and methodology of Physical design.
• Knowledge of computer architecture and Verilog/SystemVerilog.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

• Define and implement innovative methodology schemes to improve Performance, Area and Power.
• Develop all aspects of Application-Specific Integrated Circuit (ASIC) Register Transfer Level (RTL) to GDSII implementation for high Power, Performance, and Area (PPA) designs.
• Manage physical implementation for partitions.
• Work with cross functional teams to deliver best quality of results.