Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel.
- 4 years of experience in people management, developing employees.
- Experience in micro-architecture and design of Machine Learning IPs or Graphics IPs, handling Low Precision/Mixed Precision Numerics.
- Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
- Experience with programming languages (e.g., Python, C/C++ or Perl).
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing cutting-edge SoCs used to accelerate machine learning computation in data centers. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Lead a team of engineers in the Bengaluru design organization to deliver AI/ML compute intensive IPs and subsystems.
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
- Take ownership of one or more complex IPs or subsystems and implement RTL.
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Identify and drive power, performance, and area improvements for the domains owned.