Experience in extraction of design parameters, Quality of Results (QoR) metrics, and analyzing trends.

Knowledge of techniques for testing and debugging interposer designs, including electrical and thermal.

Knowledge of semiconductor device physics and transistor characteristics.

Understanding of thermal considerations for 3D stacked dies and interposers.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Own interposer routing necessary for 2.5D or 3D packaging (i.e., custom signal routing, shielding and power/ground distribution).
• Connect general purpose and high speed interfaces through an interposer with consideration for high speed effects, signal integrity, etc.
• Perform Application-Specific Integrated Circuit (ASIC) top level I/O planning and Redistribution Layer (RDL) routing.
• Perform technical evaluations of interposers, advanced packaging, process nodes, IP and provide recommendations.
• Collaborate with other design teams, including ASIC designers, package designers, and system architects on interposer layout and specification requirements, collaterals, and milestone timelines.