Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 2 years of experience with RTL design (i.e., Verilog or System Verilog) and simulation (i.e., VCS, Incisive, or Questa).
- Experience in Emulation or FPGAs for digital systems development and validation, and experience in the compile, runtime, and hosting of designs and configurations on those systems.
- Master's degree in Electrical Engineering or a related field.
- Experience in simulation acceleration using transactors (i.e., DPI-C) or vendors provided accelerated verification IP.
- Experience in a lab environment, ASIC bring-up and test development.
- Experience in performance analysis/debug techniques, and with programming/scripting skills (e.g., C, C++, Perl, TCL, Python).
- Knowledge of external I/O interfaces such as PCIe, DDR5, HBM, SPI, JTAG, etc.
- Understanding of computer architecture, including industry standard interfaces and memory subsystems.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will help architect, design, and bring up Emulation or Field-programmable Gate Array (FPGA) or Prototyping systems to serve our Silicon projects. You will work directly with other team members as well as designers, Design Verification Engineers, Validation Engineers, and software teams to deliver emulation or prototyping capabilities, including designing the testbench, monitors, or transactors for Emulation or Prototyping systems.
You will integrate daughter cards, interface adapters, host machines, or design sub-chip configurations through front-end methodologies. You will apply back-door mechanisms to speed-up runtime or take RTL through Emulation or Prototyping back-end flows, add optimizations for area/performance, debug issues in both infrastructure and design, or assist in hardware bring-up.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
- Create and support emulation models from RTL.
- Drive system bringup on emulation platforms, debug test failures and simulation/emulation mismatches.
- Bring up external I/O interfaces (e.g., PCIe, Memories, SERDES, SPI, JTAG, etc.) on the emulation platforms.
- Develop and operate tests on the emulators and assist in bring-up processes from prototyping through post-silicon validation.
- Create standalone test cases for tool issues encountered in the emulation compile and runtime flows. Contribute to ongoing methodology and automation improvements, constantly evolving and improving emulation efficiency and value.