Minimum qualifications:
- Bachelor's degree in Computer Science or related technical field, or equivalent practical experience.
- 4 years of experience in Design Verification.
- Experience verifying digital logic at RTL using SystemVerilog and UVM for ASICs.
- Experience in verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
- Experience creating and using verification components and environments in a standard verification methodology such as UVM
- Experience with GLS, low-power DV, and support of SOC DV.
- Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
- Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
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About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of complex Memory Subsystem IPs at IP and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.