Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with CPU microarchitecture.
- Experience in scripting languages like Python or Perl.
- Knowledge of high performance and low power design techniques.
- Knowledge of assertion-based formal verification.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
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Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Contribute to CPU front-end designs, emphasizing micro-architecture and RTL design for next generation CPU.
- Propose performance enhancing micro-architecture features with efficiency in mind. Work with architects and performance teams for trade-off studies.
- Deliver designs that meet power, performance, and area (PPA) goals with production quality.
- Interpret techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.