Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  
• 3 years of experience in delivering chip design infrastructure or methodology, including Multi-HDL model builds and CI/CD systems.
  
• Experience with design construction towards physical implementation, emulation, and verification.
  
• Experience working with cross-functional teams for tape-outs.
  

Preferred qualifications:

• Experience in CPU or SoC physical design, debug, and sign off flows.
  
• Experience working on complex physical design flows.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will plan and execute to work in an innovative and fast-paced environment, with a focus on infrastructure that enables design and verification teams to produce the chips that power Google's computing needs. You will be part of the chip infrastructure team responsible for compute, storage, common chip design components, and front-end tool flows. You will work with architects, logic designers, and verification engineers to develop flows to build and verify System on a chip (SoC) designs. You will also work closely with software, physical design, silicon bring-up and validation teams to enable a successful software integration, implementation, silicon bringup, and deliver quality silicon.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Plan and execute work on a chip infrastructure for back-end design and sign off flows.
• Build reusable and robust components for SoC and IP block design.
• Work with partner teams to provide the compute, storage and methodology needs of the Chip Design and Verification teams.