Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer science, or equivalent practical experience
- 3 years of experience with development projects in VLSI
Experience in RTL design, verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation
- Master's degree in Computer or Electrical Engineering
- Experience in designing or verifying digital logic using SystemVerilog for FPGAs, ASICs, and/or SoCs
- Experience in design verification technologies like UVM, simulation, coverage collection, test planning, debug, integration flows, build/release flows
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Join us to shape the future of AI/ML hardware acceleration. Work on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved worldwide. Leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a CAD/EDA/Methodology Engineer, you will plan and execute work in an innovative and fast-paced environment, with a focus on providing cutting edge flow and methodology solutions for high performance IP development. You will work with architects, logic designers, and verification engineers to develop flows to build and verify complex IPs and subsystems.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Design new RTL and/or design verification methodologies and flows for high performance IPs.
- Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.
- Be responsible to design our custom RTL and/or infrastructure solutions for IPs and hierarchical designs, and make it a delightful experience for our customers.
- Work with cross-functional teams and chip leads globally to drive changes.