ASIC SOC DFT Lead, Silicon

Minimum qualifications:

• Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience.
  
• 8 years of experience in design for testability.
  
• Experience with ATPG, low power designs, BIST, JTAG tools and flow.
  

Preferred qualifications:

• Experience working on SoC level DFT.
  
• Knowledge of high performance design DFT techniques.
• Understanding of the end to end flows - design, verification, DFT, and PD.
  
• Proficiency with Synthesis, Lint, CDC, LEC and DFT timing, and STA.
  
• Proficiency with a scripting language such as Perl.
  

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Work on a team of DFT engineers, working closely with RTL and Physical Designer Engineers.
• Work on SoC level DFT architecture.
• Write basic to complex scripts to automate the DFT flow.
• Develop tests that can be used for production in the ATE flow.
• Work with junior members of the DFT team to deliver overall deliverables for an IP or SoC.