Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in ASIC physical design and methodologies in advanced process nodes.
- Experience with place and route EDA CAD tools, commands, debug, and custom techniques via Tcl or GUI interaction.
- Experience with EMIR parameters, analysis, violation mitigation and tradeoffs related to power grid design and augmentation.
- Experience in advanced process nodes with base and metal layer DRC analyses and problem resolution.
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an ASIC Physical Design Engineer on the Chip Implementation team, you will work on the physical implementation of ASICs in advanced technology nodes.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
- Work on physical design including place and route, EMIR, static timing, and physical verification.
- Go beyond automated flow execution and use industry standard EDA CAD tools to perform custom design work, to provide customized solutions to specific problems, and to enhance PPA.