Minimum qualifications:
- Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
- 2 years of experience in design for testability.
- Experience with ATPG, Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow.
- Experience with DFT EDA Too Tessent.
- Experience in DFT for a Complex subsystem with multiple physical partitions.
- Experience with IJTAG ICL, PDL terminology, ICL modeling with Siemens Tessent Tool.
- Experience with Spyglass-DFT, and DFT Scan constraints and evaluating DFT STA paths.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work with a team of DFT engineers, working closely with RTL and Physical Designer Engineers.
- Work on Subsystem level DFT SCAN, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains.
- Write basic to complex scripts to automate the DFT flow.
- Develop tests that can be used for Production in the Automated Test Equipment (ATE) flow.
- Work with members of the DFT team to deliver overall deliverables for 2 or more complex Subsystems in a SoC.