Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- Experience in verifying digital reasoning at Register-Transfer Level (RTL) level using SystemVerilog or C/C++.
- Experience with verification components and environments in standard verification methodology.
- Experience in verifying digital systems using standard Internet Protocols (IP) components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Experience with coding languages and software development frameworks.
- Master's degree in Electrical Engineering or Computer Science, or PhD in Electrical Engineering or Computer Science, or equivalent practical experience.
- Experience in architectural background with Hierarchies, Coherency, Memory Consistency Models, Peripheral Component Interconnect Express (PCIe), Packet Processors, Security or Clock and Power Controllers.
- Experience with building verification methodologies that span simulation, emulation and Field Programmable Gate Array (FPGA) prototypes.
- Experience with performance verification of System on a Chip (SOCs), pre-Silicon analysis and post-Silicon correlation.
- Experience with Interconnect Protocols.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan and execute the verification of the next generation configurable Infrastructure Internet Protocols (IPs), interconnects and memory subsystems.
- Create and enhance constrained-random verification environments using SystemVerilog.
- Develop cross language tools and scalable verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct blocks and subsystems. Close coverage measures to identify verification holes and to show progress towards tape-out.