RTL Design Engineer
Our client in Santa Clara, CA is looking for hardworking, motivated talent to join their team. Don’t wait… apply today!
What's in it for you?
Onsite
Contract for 9 months
Full time
Job Description
JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.
KEY RESPONSIBILITIES:
Perform RTL design of digital components in Verilog/systemverilog.
Analyze/fix Lint and CDC errors of the components.
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Guarantee quality/timely deliverables meeting projects schedule.
Help to improve/automate design process.
EXPERIENCE:
7-15 years' relevant experience
Experience with RTL design integration tasks
Multi-clock domain designs.
Design constraints for synthesis and static timing analysis.
Knowledge of front-end RTL design tools and methodologies.
Knowledge of scripting languageslikePerl, tcl or cshell
Essential skills:
SOC Design integration tasks such as (RTL integration, Simulation, Debug, Synthesis, STA Constraints, scripting/automation)
Creating technical documentations such as Microarchitecture documentation, Integration guides
Nice-to-haves:
High speed serial interfaces (such as PCIe, CXL etc.)
Experience with of AXI protocol
UPF
EDUCATION: Bachelor's (required) or Master's in Computer Engineering
Why should you choose Experis?
Weekly pay with direct deposit
Consultant Care support
Free Training to upgrade your skills
Dedicated Career Partner to help you achieve your career goals
Are you Interested?
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