At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities:

• Maintain the verification test bench and test template
• Maintain the testing flows and regression framework
• Define and manage verification/test plans
• Create the reference models of DSP instructions and accelerators
• Debug the DSP instruction and accelerator tests and collaborate with design engineers
• Analyze the functional and code coverage

• Master degree in CS/CE, EE, Telecom or equivalent
• Strong knowledge of computer architecture
• Proficiency in programming languages like C/C++, assembly, Verilog
• Familiar with scripting languages like Perl, Makefile
• Familiar with design verification methodology
• Self-motivated with excellent planning, interpersonal, and communication skills
• Excellent oral and written English

• Familiar with SystemC or SystemVerilog
• Familiar with UVM
• Processor design/verification experience is highly desirable