At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Proficient in Developing STA and EMIR solutions at Full-Chip at Block Level.
(1) Hierarchical STA Flows
(2) Top Block Constraint validation and budgeting
(3) Full chip clock propagation
(4) ETM and power view model generation and validation
(5) Timing and Power Signoff checks to ensure final tapeout quality
(6) PVT Corner selection and margining for Global/Local/Library/Process/Design variations to ensure silicon success
(7) Proficient in scripting for such checks and developing flows for other members to use.
(8) Build regression suite to validate versions and features
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Client-provided location(s): Austin, TX, USA
Job ID: Cadence-R49798
Employment Type: Full Time
Perks and Benefits
Health and Wellness
- Dental Insurance
- Vision Insurance
- Life Insurance
- Short-Term Disability
- Long-Term Disability
- FSA
- HSA With Employer Contribution
- Fitness Subsidies
- On-Site Gym
- Mental Health Benefits
- Virtual Fitness Classes
- Health Insurance
Parental Benefits
- Birth Parent or Maternity Leave
- Non-Birth Parent or Paternity Leave
- Fertility Benefits
- Adoption Assistance Program
- Family Support Resources
- Adoption Leave
Work Flexibility
- Flexible Work Hours
- Hybrid Work Opportunities
Office Life and Perks
- Casual Dress
- On-Site Cafeteria
- Holiday Events
Vacation and Time Off
- Paid Vacation
- Unlimited Paid Time Off
- Paid Holidays
- Personal/Sick Days
- Leave of Absence
- Volunteer Time Off
Financial and Retirement
- 401(K) With Company Matching
- Stock Purchase Program
- Performance Bonus
- Financial Counseling
Professional Development
- Tuition Reimbursement
- Promote From Within
- Mentor Program
- Access to Online Courses
- Internship Program
- Leadership Training Program
