At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job description: Validate HDL debug tools, test automatically and help customers to clarify issues, even find workaround solutions.
Requirement: 1. MS degree or above with EE or CS background 2. Understand Verilog/VHDL or has 2+ years-experience in HDL design. 3. The experience of HDL simulator/debug tool verification is plus. 4. Familiar with Linux environment or scripts.
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