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Cadence is the leader in hardware emulation-prototyping technology and products. Looking for an experienced, well-accomplished SERDES System Validation Engineer who is interested in challenging opportunities to be a technical expert in architecture and validation of interfaces on complex high-performance emulation processing ASICs and FPGAs, and is interested in establishing SI/PI system budgets and implementing the advanced design validation of SERDES training methodologies and flows. This position is located in our San Jose headquarters office, reports to the Group Director of R&D, and works in a growing talented organization.
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Our emulation-acceleration system platform is the industry-leading, most advanced, most configurable, and most scalable system, generation after generation. These systems are primarily used in labs and datacenters. At the heart of these systems is a multitude of interconnected, highly complex, high-performance computing (HPC) units based on proprietary, innovative processor architecture. This position has a critical role in the development of such system products, and is responsible for the operation of the interconnect and interfaces of such systems.
Key responsibilities
- Be the technical SERDES expert for the system platform.
- Define and implement complex SERDES training algorithms for a complex multi-rack system involving thousands of interconnect links and a wide variety of channels on boards, in systems, over copper backplanes, and over optical fibers.
- Define and oversee the development of SI/PI design and validation methodologies for high speed electrical and optical serial link systems
- Develop validation plans for and lead the characterization and validation of SERDES and high speed memory interfaces.
- Characterize a wide range of IPs, including digital high speed serial peripherals, PLLs, and FPGAs.
- Work with SI/PI Integrity experts to approve proposed system implementations of link and power budgets.
- Work with the firmware development team for SOC characterization in order to develop in-system training and diagnostics.
- Correlate SERDES link measurement results with SI/PI budgets, and document the findings.
Qualifications
- Bachelors in Computer Science or Electrical Engineering with a minimum of 7 years of related experience, or Masters with a minimum of 5 years of related experience, or PhD with a minimum of 1 years of related experience
- Strong knowledge in high-speed system design and SI/PI budgeting methodology.
- Expertise in testing high speed serial electrical and optical links.
- Knowledge of adaptive signal processing, coding, and FEC algorithms.
- Working knowledge of PCB design and layout, as it impacts signal and power integrity.
- Experience with equalization techniques, Tx/Rx circuits, CTLE, and DFE.
- Knowledge of different CDR architectures.
- Experience in verifying DDRx/LPDDRx interfaces is a plus.
- Experience in scripting PERL, Python, or Shell is a plus.
- Technical leadership and the ability to solve technical challenges independently.
- Ability to work cross-functionally.
- Be energetic, self-driven, team oriented, and analytical
- Have good communication, organizational, project planning, and leadership skills.
The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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