At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Overview:
This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.
The candidate will primarily be responsible for leading a team of engineers in the verification of digital RTL and development of re-usable verification components and environments.
The successful candidate will be a highly motivated self-starter and with strong leadership qualities.
It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.
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The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.
The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.
The candidate should be able to work as part of a focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.
The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets.
Job Responsibilities:
- Project planning and progress tacking
- Leading team of 5-15 engineers in the execution of verification tasks
- Definition and Management of Verification Plans (vPlans) using Cadence vManager tools
- Architecture of Verification Environments for complex IP such Multi-protocols PHY
- Development of UVM-SV Scoreboards for self-checking regressions
- Development of Functional Coverage as part of Metric Driven Verification Environments
- Development of SystemVerilog Assertions for use in Formal and Simulation Environments
- Creation and Management of Automated Regression Environments, e.g. Jenkins
- Participation in Technical Review Meetings and Checklist Reviews
- Close Collaboration with Design Engineers to debug complex test scenarios
Job Qualifications:
- Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
- 12+ years' experience in microelectronics/EDA industry
- Experience of Verilog RTL Design essential
- Experience of Metric Driven Verification (MDV) essential
- Excellent oral and written English essential
- Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
- Self-motivated with excellent planning, interpersonal, and communication skills
Additional Information:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Travel: < 5%
Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success.
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We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.