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Senior Principal Design Engineer - Systems and Interfaces

San Jose

Job Description:

The Cadence Compute Systems Group (CSG) develops and licenses IP designs for SoC and ASIC systems. This includes high-performance DSPs, CPUs, Interface IP, DDR controllers, hardware accelerators, and subsystems. Our cutting-edge compute engines enable applications such as Machine Learning, Edge AI, Radar, Audio, Speech, and Vision. Our IP designs are used by leading semiconductor developers and companies, and our customers are shipping billions of chips annually using our products.

The CSG Central Applications Engineering team seeks an experienced SoC design engineer to integrate and support Cadence IP products in system reference designs. This Systems CAE will use advanced system design tools to integrate and validate reference designs using compute, memory, and interface IP components.

• Become the CAE expert on Cadence Interface I/O controllers and IP integration.
• Develop examples and best practices for SoC system design, verification, and testbenches for CSG IP.
• Write documentation, application notes, and system design and verification examples.
• Lead the evaluation, review, and advanced usage of new products for release.
• Develop customer training and help train customers and field application engineers on Cadence IP, interfaces, system verification, and EDA flows.
• Work closely with the Cadence customer support team and answer advanced questions on our products. Interact directly with customers as needed.
• Analyze and propose enhancements to our products, software tools, and documentation to better serve customer use cases.

• Extensive knowledge of interface protocols, including Ethernet, PCIe, MIPI, USB, and UCIe.
• Design and verification experience with high-speed I/O interfaces.
• Experience in IP integration, SoC system architecture, interfaces, and interconnects.
• Experience in configuring and optimizing Network-on-Chip interconnects.
• Experience with interconnect protocols such as AMBA (ACE, CHI, AXI, AHB, APB) and on-chip trace and debug (JTAG, CoreSight).
• Proficient in writing and debugging RTL (Verilog, System Verilog).
• Experience in RTL synthesis and static timing analysis is required.
• Strong written and oral communication skills are required.
• A BS in EE/CS with 10+ years of work experience or an MS in EE/CS with 4+ years of work experience is required.
• Some travel (up to 10% of the time), including international travel, is required.