Senior Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are a great and passionate engineering team building the next Palladium Emulation ASIC and system at Cadence Design System.

Palladium has been the leader in the industry over the past 20 years and we are pushing the envelope using the latest technology node and methodologies.

Palladium is a massively parallel system with 1000s of custom processors tightly interconnected together through a custom and proprietary mesh using the latest tools and IPs from Cadence.

Key Responsibilities

• Will be responsible for developing and debugging design constraints across all modes and level of hierarchies (block / subChip / top)
• The candidate will routinely discuss with Design team to facilitate logic changes and improved / drive timing to closure.
• The position will interact with both Front End (Design / DFT) and Back End Implementation Teams (P&R).
• Proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.
• Experience with large design STA and Timing Closure.
• Familiar with ECO techniques and implementation.
• Maintain scripts and methodologies for analysis and runs.
• Implement timing infrastructure.

• BS in electrical or computer engineering with a minimum of 10 years of ASIC Design experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Excellent written and verbal communication skills.
• Understanding of complete SOC design and flow.

• Self-motivated team player with strong problem-solving and analytical skills to collaborate with various teams to achieve desired goals
• Experience in at least one scripting language like PERL, Python, Tk/TCL or Shell is preferred.