At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Design Verification role for IP development team.
Position is based in Bangalore, part of Cadence IP Group. Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
In addition to UVM functional verification, role could involve Formal verification of complex design modules.
In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
Understand design and produce detailed verification strategy and test plan.
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