Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This team is focused on High Speed Serdes. The ideal candidate will have at least 5 plus years of actual work experience in SerDes as well as a thorough understanding of the end-to-end digital design flow to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to:

• Digital microarchitecture definition and documentation
• RTL logic design, debug and functional verification
• Understanding of digital architecture trade-offs for power, performance, and area
• Understanding of proper handling of multiple asynchronous clock domains and their crossings
• Understanding of Lint checks, UPF checks and proper resolution of errors
• Understanding synthesis timing constraints, static timing analysis and constraint development
• Understanding of fundamental physical design flows and stages
• Understanding of wireline standards and collaborating with standards experts to relate standard requirements to logic specifications
• Experience on silicon bring-up and testing of wireline IP
• Strong background in DSP and algorithms is a plus

• Master's degree or higher in Electrical Engineering
• Minimum 5 years of digital design work experience
• Hands-on experience in implementing and demonstrating digital designs in FPGAs or ICs