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Job Description: This position is in Cadence Pegasus Physical Verification R&D team in Hsinchu, Taiwan. The candidate for this position will be developing design rule check (DRC) and FILL decks for advanced nodes of semiconductor manufacturing, The job involves creating quality check (QC) patterns, writing physical verification DRC and FILL rules and developing decks consisting of these rules. It also involves testing these decks on real customer designs and troubleshooting the deck and tool issues, providing feedback to Pegasus Foundry Team, Pegasus R&D, and foundry partners.
Requirement: At least 2 years of previous experience with DRC or FILL deck development, and BS or MS degree in engineering.
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