At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Lead Solutions Engineer: Digital Design - RTL and Synthesis to work with us in Brazil.

As a Lead Solutions Engineer: Digital Design - RTL and Synthesis, you will be part of the Silicon Engineering team. In this role, you will work with an experienced Cadence team and leading-edge customers to implement SoC designs in advanced process nodes. You will use Cadence's market-leading technologies to design RTL of digital IPs, perform simulation and synthesis to help customers turn their design ideas into products that will be deployed in the marketplace.

• Perform the digital design of SoC IPs from high-level architecture to synthesis according to customer technical needs;
• Create micro-architecture specification;
• Develop RTL and SystemC;
• Define functional constraints and synthesize the RTL to guarantee that the design met the power, performance and area requirements;
• Support the verification and validation teams, participating in the test plan definition, coverage analysis and features debug;
• Support the physical design team to ensure that the constraints are correct and that the design is feasible to be physically implemented;
• Provide mentorship for less experienced team members.

• Complete Bachelor's degree in Computer/Electrical Engineering or related areas;
• Strong knowledge of digital design and semiconductor fundamentals;
• Ability to design digital IPs autonomously ensuring that the IPs are delivered on time;
• Solid knowledge in designing IPs and/or integrating SoCs;
• Strong knowledge in SystemVerilog and/or SystemC;
• Solid knowledge in simulation and debug tools;
• Solid knowledge in functional constraints definition;
• Solid knowledge in logical and physical synthesis;
• Solid verbal and written skills and collaboration capabilities;
• Experience in scripting languages (Python, TCL).

• Knowledge in low power design and techniques;
• Knowledge in logical equivalence checking;
• Knowledge in clock and reset domain crossing;
• Strong knowledge in Cadence's front-end tools (Xcelium, VerisiumDebug/Simvision, Genus, Joules);
• Experience with Cadence's physical synthesis tool (Genus and Innovus);
• Knowledge in the DFT flow.

• Employment category: CLT
• Employment term: 40 hours/week.
• Hybrid work.
• Competitive benefits.