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Be part of the Cadence DDR PHY IP Front End Design team responsible for -
Developing firmware for DDR PHY using microcontrollers
Responsible for developing firmware in C and similar Embedded programming languages typically involving bare-metal programming and developing low-level APIs on Microcontrollers.
Responsible for collaborating with hardware designers and memory subsystem architects to derive algorithms and implement them.
Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.
Support debug of firmware-based simulations in hardware behavioral simulations (RTL simulations with firmware for verification)
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