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Job Description:

• To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.
• PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout.
• Responsible for physical verification methodology, including installation, development, qualification, automation, and support -
  • To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows.
  • And to support layout teams in verification flow issues.
• Ensuring QA of the integrated PDK's with the custom design environment

• Add sub scripts to improve efficiency on QA process with adequate coverage.

• Bachelor's Degree in Electrical/Electronic Engineering or equivalent .
• 4-7 years of Work experience in PDK development and CAD enablement.
• Expertise in Cadence Python, SKILL, Perl programming languages.
• Knowledge of deep sub-micron CMOS processes, device physics and layout design.
• Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
• Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting.
• Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus.
• Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc)
• Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus
• Excellent technical problem solving skills.
• Excellent communication and presentation skills.