At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is the leader in hardware emulation-acceleration technologies and products. Physical Design Hardware Engineering Director will be responsible for leading physical design implementation of family of very large ASICs in latest technology nodes. This individual must be a dynamic "hands-on" leader who will oversee end to end physical design of chip to tapeout, while developing and growing the team. The Director will also identify and lead major initiatives as we continue to scale up and innovate. This person must have a strong technical background in leading large, highly complex chip projects. This position is located in our US offices (San Jose, CA or Raleigh, NC) and reports directly to the Vice President of Engineering.
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Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters. At the heart of these systems are a multitude of interconnected highly complex high-performance computing (HPC) devices based on a proprietary Boolean processor architecture. This is a role in the core technology team.
Key Responsibilities:
The duties and responsibilities of the Group Director of Hardware Engineering include:
- Lead a talented team of highly accomplished internationally dispersed Place and Route (P&R) physical design engineers
- Hands on top level floorplan, block partitioning and push down, pin placement, high speed clock tree design, place and route, post-route optimization, timing closure, physical verification, IR drop analysis and sign off, and tapeout for premier HSV products
- With backend driven frontend design implementation in mind, work closely and iterate with architecture, frontend and middle end design teams for optimal design solutions and implementation
- High speed custom clocking and high speed signal intensive routing and mesh design experience
- Work as a team member with peers and across organizational boundaries to build alignment and resolve issues
- Participate in the definition of the technology strategy and roadmap to support the business goals
- Drive strategic technological innovation, develop and grow the team locally and internationally
- Model and reinforce the Cadence Design culture and core values
- Act as an agent of change to instill the culture of high performance, collaboration and innovation.
Qualifications
- Top level chip implementation experience a must
- Experience leading place and route engineering teams to build large, high speed, complex chips on 3nm or below technology nodes
- Experience managing geographically dispersed engineering teams
- Sense of accountability
- Ability to think strategically and also to proactively roll up sleeves and get things done.
- Ability to actively motivate and inspire. A true coach and mentor.
- Demonstrated strong analytical mindset and ability to think outside the box.
- Must be passionate about technology and highly technical
- A minimum of 15 years in a related position
- PhD or MS in Computer Science, Electrical Engineering, or related disciplines.
Preferred Technical and Professional Experience
- Hands-on experience in most aspects of chip design: microarchitecture, RTL, verification, physical design, post-silicon validation, etc.
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