At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence's Genus Synthesis Solution is a product which takes a high-level description of a microchip - that is expressions of the form "x = (a + b) × (a - b)" or "y = c + (s ? d - e : 0)" - and synthesizes all the NAND, NOR, XOR, etc. gates needed to build the circuit. Since there are many possible circuits that will achieve the same results Genus works hard to find a solution which is best for maximizing clock speed, minimizing chip size and/or reducing power - depending on the users' requirements.

The algorithms owned by the Genus Datapath Optimization Team sit at the beginning of this process, and operate directly on fundamental operators, such as adders, multipliers and muxes. For example, it would usually (but not always) be better to replace "x = (a + b) × (a - b)" by "x = a² - b²". Making such architectural optimizations at the beginning of the flow can have a bigger impact on the quality of results than can be achieved in subsequent steps - where the optimizations are applied at a gate level. Therefore, there is huge opportunity to innovate and deliver significant value to our customers.