At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The intern will be a member of the Tensilica DSP Group within Cadence.

The DSP Core Group designs, and releases state-of-the-art DSP Cores to the industry focusing on defining ISAs and microarchitectures to accelerate DSP and AI algorithms for the Audio/Voice/Speech, Vision/Imaging and Radar/Lidar/Communication applications for Consumer and Automotive markets.

Responsibilities include:

• Work closely with the design team as part of the verification and modelling team.
• Develop behavioral models and tests in C.
• Develop system Verilog testbench and assertions.
• Assist with developing test plans, debugging failures, and analyzing coverage information.

• Interact with HW and SW architects and micro-architects for the verification in the context of the DSP Core products.

• Currently pursuing MS CS,CE, EE, or equivalent
• Knowledge of computer architecture
• Knowledge of Verilog and System Verilog

• Proficiency in programming languages like C/C++, assembly, Verilog
• Familiar with scripting languages like Perl, Makefile.
• Familiar with design verification methodology
• Analytical skills and problem-Solving abilities
• Self-motivated with excellent planning, interpersonal, and communication skills
• Excellent oral and written English
• Eager to learn and participate in the development of state-of-the-art DSP Core products.