At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
CPU Hardware Design Intern (Summer 2025)
The role of Hardware Design Intern will assist in the development of the new RISCV vector core.
Tasks will include but not limited to the following :
Assist in debugging and fix design issue in the vector engine
Developing specific tests to target boundary conditions in the design
Help analyze and fix timing issues with the new vector design
Explore alternative implementations for complex vector instructions.
In addition, the intern will have their own design project.
This will be limited to a subsection of the vector instruction set.
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Tasks will include :
Micro-architecting their subunit
Initial RTL entry
Testing their own design with our existing testbench
Explore area/timing trade offs for their design
Requirements:
Currently enrolled in BS or MS in EE, CE, ECE, or equivalent.
Deep understanding of Digital Design and/or Design Verification Fundamentals
Exposure to design automation tools is a plus
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