Position:
Physical Design Engineer | eInfochips

Job Description:

eInfochips - An Arrow Company (www.einfochips.com) is a pure-play Product Engineering Services company, with focus on product innovation and solution accelerators to the $60 billion (2015) Global Engineering & R&D Services Market. eInfochips provides solutions across the product stack - Silicon, Hardware, Embedded Software, Applications, Industrial Design and User Interfaces.

eInfochips has over 1700+ professionals, world-class processes and infrastructure spread across 8 delivery centers in Ahmedabad (HQ), Pune, Bangalore and Chennai. The Company has been debt-free, cash-positive and has shown 20%+ Y on Y growth over the past 4 years.

• Senior Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR Flow
• Executing the block level place and route assignments from Netlist through GDS flow
• Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII) , but it is not must.
• To close STA timing across all corners and modes for blocks and should be able to generate ECO independently
• Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing
• Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII
• To ensure successful delivery of his block(s) to customers

• Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry
• Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player
• Hands-on experience with Place and Route tools (Synopsys - ICC , Cadence - Innovus / Encounter) is a must
• Experience on latest technology (28nm,16nm,7 nm)
• 2+ years Experience in this field