Summary

Posted: Jan 6, 2025

Role Number:200585553

At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and uncommonly hardworking RTL Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. In this role, you will have the opportunity to specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side).

Description

In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions, debugging code, and otherwise interacting with the design verification team. Additionally, you will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.

• BS degree in technical discipline with minimum 10 years of relevant experience.

• Deep knowledge of mixed signal concepts
• Deep knowledge of RTL design fundamentals (control and data path).
• Deep knowledge of Verilog and SystemVerilog.
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, unified power flow, logic equivalence checkers).
• Working knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production test).
• Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques.
• Deep knowledge of scripting languages. Perl and Python are plusses.
• Deep knowledge of Algorithm developments.
• Strong communication and presentation skills.
• SERDES architecture knowledge is a plus.

• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.