Summary

Posted: Oct 28, 2024

Role Number:200576041

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. We are looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role, and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today! Your efforts will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.

• BS and a minimum of 3 years of relevant industry experience.

• We are looking for applicants with experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
• Ideal candidate will have hands-on experience in PPA ( Performance, Power, Area) analysis for different Physical designs and evaluate new Stdcell libraries in leading tech nodes.
• Familiar with development of block/partitions for silicon validation of foundation IPs.
• Good understanding of Place-and-Route design as well as associated tools/flow, ability to analyze physical databases and drive new ideas.
• Experience with industry standard synthesis, physical design and STA tools.
• Familiar with ASIC integration flows, including power distribution, global signal planning, I/O planning and hard IP integration is highly desired.
• Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure is preferred.
• Hands-on experience with ECO implementation, both functional and timing closure is helpful.
• Familiar with DFT insertion, and multi-mode timing constraints is a strong plus.
• Strong scripting skills using Perl/Tcl.
• Strong written/verbal communication skills.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $136,300 and $248,700, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.