Summary

Posted: Aug 26, 2024

Role Number:200470550

Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Engineering group, you'll help design and manufacture our next-generation, high-performance, power-efficient processors! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. As part of the GPU FE Implementation team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!

Description

The successful candidate will work closely with the RTL and PD (physical design) teams and be responsible for synthesis, analysis, and optimization of the delivered IP. For this role, use and develop advanced techniques to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Through this collaboration, you will deliver the best-in-class GPU's for the best consumer products. If you're ready to help chart the future of Apple Silicon, we'd love to talk to you.

• We seek highly motivated individuals with expert synthesis design experience that understand RTL design principles and can drive quality physical design implementation.
• Own block level synthesis and drive analysis and optimizations using advanced synthesis techniques and RTL design improvement for optimal Area, Timing Power.
• Collaborate with Physical Design and Timing Analysis teams on physical concepts like floor-planning, placement, congestion, and timing constraints.
• Analyze architectural critical paths and drive multi-block closure across RTL Design and Physical Design teams.
• Debug complex logic equivalence issues and reviewing netlist checks to validate functionality and netlist quality.
• Demonstrated ability to solve complex problems across multiple technical domains.
• Develop and Drive adoption of innovative methodologies across projects and teams
• Experience implementing ECOs for functionality and timing.
• Experience with one or more of: reset domain, multi-clock domain, multi-power domain (UPF), linting tools across RTL and Gate-Level.
• Relevant scripting experience in ASIC flows - python, tcl, Perl, Data manipulation.
• Preferred, but not required:
• Familiarity with DFT insertion.
• Familiarity with simulation, debugging tools and experience of working closely with design verification team.
• Experience working on GPUs is desirable.

• Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.