Summary
Posted: Jul 31, 2024
Role Number:200453770
Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU! You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions! Joining this group means crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for realizing the complete electrical analysis closure from early design planning to tapeout.
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Description
• Work closely with the Physical Design team to design power grid specification that achieves the best balance between power integrity targets and PNR performance, power and Area (PPA). • Drive definition of on-die power switch topology, wake-up schemes, and in-rush control. • Collaborate with internal teams to drive bump map, custom RDL routing, and package design/optimization. • Develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges. • Perform Power Integrity, EM, and ESD analysis, drive feedback, and recommend design solutions. • Drive the work among PD and Analysis engineers to set goals, plan short and long-term work comprehending dependencies between different domains like top, STA, block place and route. • Communicate and drive the needs of PD and Electrical Analysis with multi-functional teams that will enable achieving the goals of the back-end design for the project.
- Deep experience planning, implementing, and analyzing power delivery networks. Emphasis will be with on-die high frequency power delivery, but exposure to off-die concepts and models is required.
- Expertise working with different types of power-gated delivery techniques are crucial, including distributed and ring methods.
- Experience with bump planning and redistribution layer routing strategies, including methods for working with IO bumps and edge encroachment scenarios.
- Experience with fundamentals of Signal/Power Integrity checks for Electromigration and Static Noise checks.
- Background with Power Integrity analysis methodologies including Static IR and Dynamic Voltage drop checks, involving both Vectorless and Vectored approaches.
Preferred Qualifications
- We value a consistent record in all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning, and hard IP integration.
- Depth of expertise with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative technologies.
- Experience with in-rush current analysis and mitigation techniques recommended.
- Circuit design and simulation background a plus, but not required.
- Experience in technical project leadership and getting results that have had impact on project completion and objectives.
- Track record of applying creative thinking to strategically solve problems that have impact for a project, group, or organization.
- Consistent record in solving complex PD and multi-functional problems, achieving results directly and/or leading a team of engineers to innovate and achieve extraordinary GPU designs.
- From a CAD tool perspective, prior experience with power integrity tool (e.g. Redhawk, Voltus) is required. Additional experience with timing verification, SPICE simulation/analysis, and Physical Design Verification Flows are a plus.
- B.S. degree and minimum of 10 years of relevant experience.
Education & Experience
Additional Requirements
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- Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.