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We are looking for ASIC Design Verification Engineer to provide design verification services for complex multi-CPU/DSP SoC on the most advance technology notes.

• Develop test plans, tests and verification infrastructure for verifying DSP blocks.
• Build verification environment using SV/UVM methodology
• Build reusable bus functional models, monitors, checkers and scoreboards
• Drive coverage driven verification closure
• Regression triage.
• Work with architects, designers and post-silicon teams.
• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

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Qualifications

Here's what you need:

• Bachelor's Degree or equivalent (12 years) work experience (If an, Associate's Degree with 6 years of work experience)
• 1+ years ofexperience in SoC Design Verification and HW/SW verification

Bonus Points if:

• Proficient in System Verilog and C/C++.
• Strong coding skills in Perl or other industry-standard scripting languages
• Proven knowledge/experience with industry standard verification tools for simulation and debug
• Confirmed debugging and strong analytical skills.
• Knowledge of System Verilog UVM and vertical test-bench integration
• Knowledge of low level HW/SW interaction and debug
• Knowledge of multi-CPU and debug architectures
• Experience with development of fully automated flows
• Integration/development of UVM mailboxes and HW/SW communication components
• Integration of lower level UVM testbenches
• Test plan development
• Experience on DSP-heavy design verification at SoC level or IP level.
• Familiar with Matlab vector-based verification.
• Experience or domain knowledge; AXI, APB, Pre-silicon functional verification using ARM processor
• Deep knowledge of System Verilog and UVM.
• Experience with hardware emulation and FPGAs.
• Experience with Gate Level Simulations
• Experience with RISC-V architecture
• Experience with coresight architecture

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